You do not have the required permissions to view the files attached to this post. Last edited by danhans42 on June 18th, , pm, edited 3 times in total. I was going to see if I could get Xflash to detect them. Only changes are the 6 lines with the suggestions from Trimesh. Re: Compiling X-Flash Post by Shadow » March 31st, , pm We'll have to definitely make an official release with all the needed fixes and adjustments in place sometime.
Good to see it being able to be compiled though. That's always a good sign. Re: Compiling X-Flash Post by danhans42 » April 1st, , am Think we do need to update it, completely open of course. Had a further play with this. Pre-flashed it with Caetla 0. I will get a screenshot of it and upload the modified code later today , it does write something to the ROM as it wont boot after the attempt.. There are three settings in the code that I changed.. Anyone help with the block size? Is this page size?
Ill see about getting the latest version into github, so the changes can be tracked easily from the original code. I have also uploaded both the datasheets for convenience. Re: Compiling X-Flash Post by danhans42 » April 1st, , am Ahaaa,, amazing what you find when you read things correctly Re: Compiling X-Flash Post by danhans42 » April 1st, , pm Looks like it might be worth looking at the SST 28SF, as it supports byte write and sector erase possibly similar to the flash operation of the 39F Investigation continues Will work on pushing this to github tonight.
Will keep the versioning the same but this can become v1. If anyone has any unsupported flash parts they would like me to try and add, please let me know. I would need to know the ID numbers that xflash displays to code it in.
Re: Compiling X-Flash Post by danhans42 » April 2nd, , pm Had a look after the failed write,, seems that it writes one byte per h bytes Ill post the files for comparison later. Tried with different page sizes and that didnt work. Writes something every h bytes.. Have also added the source and compiled EXE.. If anyone UK or elsewhere has any bricked carts they want fixing that arent supported please get in touch..
The x8 option of this product family will only be available in lead TSOP and Additional information on this product family can be obtained by. Verify with your local Intel sales office that. Order Number: October Revision History. Original version. Section 3. Program and Erase Suspend Latency specification change.
Minor wording changes. Combined byte-wide specification previously with this document. Improved speed specification to 80 ns 3. Improved 1.
Improved several DC characteristics Section 4. Improved several AC characteristics Sections 4. Combined 2. Removed ns and ns speed offerings. Moved Ordering Information from Appendix to Section 6. Moved Additional Information from Appendix to Section 7. Updated figure Appendix B, Access Time vs.
Capacitive Load. Skip to main content Skip to sections. This service is more advanced with JavaScript available. Advertisement Hide. Data Remanence in Flash Memory Devices. Authors Authors and affiliations Sergei Skorobogatov. Conference paper. This process is experimental and the keywords may be updated as the learning algorithm improves. Download to read the full conference paper text.
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